SoC Overview

All SoC designs include the following peripherals by default:

Base: GPIO(2), SPI(1), TIMER(3), PWM(3), UART(1)

If multiple instances are possible, the maximum number of units configured for this SoC are listed in brackets.

SoC ID CPU/Arch SCACHE IRQ Peripherals DMA Reference platform License Applications
agathe Zealot/ZPU n 1 PWM(8) 0 (1) OS Configuration µP
agneta ZPUng v1 y 4 EFB MACHXO hardened IP 0 (1) C Multi I/O PWM control
bertram ZPUng v1 y 4 PWMPLUS 0 (2) C Multi LED strip controller
dombert ZPUng v1.1 n 4 CPK, JPEG, MAC,  DMAA 2 (3), (4), (5)  CS MJPEG encoding/streaming SoC
dagobert ZPUng v1.1 y 6 MAC, PWM(3), DMAA 2 netpp node CS netpp/UDP SoC (Analog I/O)

License codes:

OS: OpenSource, C: Source available under Custom agreement, CS: Closed Source, N/A: under development

Third party reference platforms

  1. Mach XO2/XO3 breakout board [Link]
  2. Papilio Spartan3 250k [Link]
  3. Lattice HDR60 camera eval platform [Link]
  4. Lattice Versa ECP5G eval board [Link]
  5. Trenz TE0600 based custom eval board [Link]

Development kit

Peripheral IP Cores:

  • SCACHE: Virtual ROM (SPI cache). Enhances program memory up to several MB of ROM code for program overlay or data storage
  • DMA/DMAA: Simple DMA/Autobuffer DMA engine for high speed transfers with little CPU interference
  • LCDIO: Custom LCD driver engine
  • SPI: 32 bit word capable SPI I/O, DMA capable on d* SoCs.
  • TWI: proprietary i2c peripheral (with clock stretching)
  • PWMPLUS: Improved PWM for realtime pulse width control
  • FX2FIFO: Cypress FX2 FIFO interface for fast isochronous data transfer
  • MAC: Ethernet MAC interface for RGMII or GMII capable Phy Circuits
  • CPK: Proprietary image processing pipeline ‹COTTONPICKEN›
  • SPORT: Fast serial port for audio codec I/O, DMA capable
  • JPEG: JPEG hardware encoder
  • FLiX: proprietary microcode engine for DSP applications (ZPUng v2 only)


Reference SoC details


  • Zealot (Opensource) CPU
  • Family supply for MACHXO2, Spartan3, Spartan6

License: OpenSource for eval

Reference applications:
  • Simple but slow (minimum 4 clock cycles per operation) configuration processor for i2c devices
  • Protocol translator from multiple i2c sensors to UART
  • PWM controller

agneta, beatrix/bertram

  • ZPUng (proprietary section5) CPU, pipelined, 1 cycle per op
  • Family support for MACHXO2, MACHXO3 (a* families), Spartan3, Spartan6, ECP3 (a* and b* family)

License: Proprietary non-OpenSource, Sourcecode licenseable

Reference applications
  • Safety relevant IoT applications (netpp on FPGA)
  • Multi channel WS2812B LED strip control through PWMPlus IP core
  • TFT/LCD display interfacing


The dombert SoC is considered a ZPUng based backport of the no longer maintained PyPS ‹dorothea› SoC. It requires approx. half of the logic elements and runs at a higher speed, although the ZPUng execution speed is slower. We are currently in process of verifying all previous functionality. Working:

  • MJPEG streaming
  • DMAA engine
  • 100M Ethernet stress test passed

The 1000 Mbit setup on this SoC is usable up to 50 MByte/s, but turned out to require an architectural change for full throughput. This will be forked off into a ‹emil› configuration (not yet documented, available as custom design service).

  • HDR60 MJPEG streaming reference design (Demo) [ english ]


The dagobert SoC is a specific edition for the netpp_node development kit and is a dombert derivative with improved high speed streaming options for real time systems.

  • High speed UDP Ethernet network stack
  • DMAA engine
  • 32 I/O pins with pin multiplexing options
  • SPI data/program cache for user storage

Reference applications: netpp IoT stack with UDP/IP, ARP and ICMP support

  • Fact sheet [ english ]
  • Preliminary developer reference available on request

Legacy SoC designs

These SoC designs are frozen and no longer maintained. Only listed for reference.


No longer maintained, all new developments is merged into bertram.


No longer maintained. All ‹cordula› development is merged into the new ‹dombert› SoC configuration.


The dorothea SoC (based on the legacy PyPS core) is superseded by the alpha development stage dombert SoC using the ZPUng v1.1 architecture. It is meant to be the full drop-in replacement for the dorothea MJPEG/h264 accelerator and streaming engine (see dombert SoC below)


The cranach design is frozen at v0.2 (updates no longer maintained) and is superseded by ‹dagobert›.